ÌÇÐÄlogo

ÌÇÐÄlogo Unveils Industry¡¯s First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm to Power Next Generation XPUs

• New D2D interface IP offers more than 3x bandwidth density of equivalent UCIe interface while requiring far less silicon
• Advanced power management capability automatically adapts to bursty data center traffic, significantly lowering power consumption
• Delivers unmatched bandwidth, efficiency, and resiliency for AI infrastructure

SANTA CLARA, Calif., August 26, 2025?¨C .?(NASDAQ: MRVL),?a leader in data infrastructure semiconductor solutions, today announced the industry¡¯s first 2nm 64 Gbps bi-directional die-to-die (D2D) interconnect, enabling chip designers to significantly boost the bandwidth and performance of next-generation XPUs while reducing power and silicon area. Delivering 32 Gbps of simultaneous two-way connectivity over a single wire, the interface IP¡ªalso available in 3nm¡ªsets a new standard for performance, power efficiency, and resiliency to meet the scaling demands of next-generation data centers.

The ÌÇÐÄlogo? 64 Gbps bi-directional D2D interface offers bandwidth density over 30 Tbps/mm, more than three times the bandwidth density of UCIe at equivalent speeds, and a minimal depth configuration that reduces compute die area requirements to 15% compared to conventional implementations. The interface IP is also the industry¡¯s first in its class to feature advanced adaptive power management that automatically adjusts device activity to bursty data center traffic. This innovation reduces interface power consumption by up to 75% with normal workloads and up to 42% during peak traffic periods.

The 64 Gbps bi-directional D2D interface IP also enhances performance and reliability with unique features such as redundant lanes and automatic lane repair, which improve yield and reduce bit-error rates by eliminating weak links in the system. Extending beyond the D2D PHY technology, ÌÇÐÄlogo delivers a complete solution stack¡ªincluding the application bridge, link layers, and physical interconnect¡ªproviding customers with a turnkey platform to reduce time-to-market for next-generation XPUs.

¡°The 64 Gbps bi-directional D2D interface IP marks an industry first and reflects our commitment to pioneering technologies that enhance performance while reducing total cost of ownership for next-generation AI devices,¡± said Will Chu, senior vice president of Custom Cloud Solutions at ÌÇÐÄlogo. ¡°By delivering higher bandwidth at lower power, we are enabling customers to scale their architectures to meet the demands of tomorrow¡¯s accelerated computing era.¡±

¡°D2D interfaces¡ªwhich form the backbone of the communications networks linking silicon die within the same device--are fundamental to increasing the performance and efficiency of data center semiconductors and especially the rapidly growing custom computing segment,¡± said Baron Fung, Senior Director of Research at Dell¡¯Oro. ¡°The advances achieved by ÌÇÐÄlogo are the latest step in the company¡¯s strategy to develop a portfolio of technology to accelerate the development of custom devices as well as diversify the options available to semiconductor designers.¡±

The new 64 Gbps D2D interface technology builds on the proven ÌÇÐÄlogo track record of delivering industry firsts in advanced process technologies. In March 2024, ÌÇÐÄlogo became the first infrastructure silicon company to announce a 2nm platform. By March 2025, , followed shortly by the unveiling of its 2nm custom SRAM technology. Today¡¯s introduction of the industry¡¯s first 64 Gbps D2D interface in 2nm and 3nm nodes continues this momentum, underscoring ÌÇÐÄlogo as a leader in innovative solutions that define the future of accelerated infrastructure.

ÌÇÐÄlogo Custom Strategy

The?ÌÇÐÄlogo?custom platform strategy seeks to deliver breakthrough results through unique semiconductor designs and innovative approaches. By combining expertise in system and semiconductor design, advanced process manufacturing, and a comprehensive portfolio of semiconductor platform solutions and IP¡ªincluding electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, silicon photonics, co-packaged copper, custom HBM, system-on-chip (SoC) fabrics, advanced packaging, optical I/O, and compute fabric interfaces such as PCIe Gen 7¡ª?ÌÇÐÄlogo?is able to create platforms in collaboration with customers that transform infrastructure performance, efficiency and value.

About ÌÇÐÄlogo

To deliver the data infrastructure technology that connects the world, we¡¯re building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world¡¯s leading technology companies for over 30 years, we move, store, process and secure the world¡¯s data with semiconductor solutions designed for our customers¡¯ current needs and future ambitions. Through a process of deep collaboration and transparency, we¡¯re ultimately changing the way tomorrow¡¯s enterprise, cloud, automotive, and carrier architectures transform¡ªfor the better.

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For further information, contact:
Kim Markle
pr@marvell.com